The invention relates generally to solid-state switching and amplification devices. More particularly, the invention relates to a transistor having passivated metal-semiconductor junctions from the source to the channel and/or from the channel to the drain and at which the Fermi level of a semiconductor which comprises the channel is depinned.
One of the most basic electrical junctions used in modern devices is the metal-semiconductor junction. In these junctions, a metal (such as aluminum) is brought into contact with a semiconductor (such as silicon). This forms a device (a diode) which can be inherently rectifying; that is, the junction will tend to conduct current in one direction more favorably than in the other direction. In other cases, depending on the materials used, the junction may be ohmic in nature (i.e., the contact may have negligible resistance regardless of the direction of current flow). In addition to diodes, such metalxe2x80x94semiconductor junctions are also present at source/drainxe2x80x94channel interfaces within a class of transistors known as MOSFETs (metal oxide semiconductor field effect transistors).
As explained in the above-cited patent application, there exists at a metal-semiconductor contact a so-called Schottky barrier. The Schottky barrier at a conventional metal-semiconductor junction is characterized by Fermi level pinning of the semiconductor, due to both extrinsic and intrinsic surface states. The extrinsic states may arise from defects in the crystal structure of the interface. The intrinsic states arise from the quantum-mechanical penetration of the electrons in the metal into the bandgap of the semiconductor. These so-called metal-induced gap states (MIGS) appear to be of fundamental importance in explaining the physics of such junctions. See J. Tersoff, xe2x80x9cSchottky Barrier Heights and the Continuum of Gap States,xe2x80x9d Phys. Rev. Lett. 52 (6), Feb. 6, 1984.
The Schottky barrier height at a metal-semiconductor interface determines the electrical properties of the junction. Thus, if it were possible to control or adjust the barrier height of a metal-semiconductor junction, electrical devices of desired characteristics could be produced. To tune the barrier height, the Fermi level of the semiconductor must be depinned. As discussed in detail in the above-cited patent application, the present inventors have achieved this goal in a device that still permits substantial current flow between the metal and the semiconductor. Below, the inventors present an application of this technology to MOSFET devices.
MOSFETs which incorporate Schottky junctions have a longxe2x80x94and largely unfruitfulxe2x80x94history. In 1966, Lepselter and Kahng were investigating Schottky diodes. In that year they received U.S. Pat. No. 3,290,127 directed to a device with a PtSi/Si interface. Use of the silicide was found to be an improvement over previous metal/Si contacts. The diodes were reproducible and stable, in part because the interface was sealed, as noted by the inventors at the time. The silicide also may reduce the extrinsic surface states (defects). The remaining pinning is most likely due to intrinsic surface states (MIGS), although this was not recognized at the time. Shortly thereafter, Lepselter and Sze incorporated the Schottky barrier into a MOSFET (see M. P. Lepselter and S. M. Sze, xe2x80x9cSB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts as source and drainxe2x80x9d, Proc. IEEE 56, 1088 (1968)). U.S. Pat. No. 3,590,471 to Lepselter discussed the incorporation of the Schottky barriers, but the channel was still essentially isolated by implanted regions. The first patent for a channel isolated by Schottky barriers (U.S. Pat. No. 3,708,360) was issued to Wakefield and Cunningham in 1973. This device also utilized silicided junctions.
In U.S. Pat. No. 4,300,152, Lepselter described a Schottky barrier MOSFET. By eliminating the pn-junction in the source-substrate region, Lepselter showed that the parasitic pnpn structure responsible for latch-up could be eliminated. The proposed devices still utilized PtSi for the source and drain metal, however.
An extension of Lepselter""s early work is found in U.S. Pat. No. 4,485,550 to Koeneke et al. In these devices, an extra implant is added to extend beyond the source metal. This is similar to modern CMOS halo implants. The extra implant improves the drive current capabilities of the transistor by bringing the channel edge under the gate. The channel isolation in this device is from a pn-junction, not the PtSi source metal. An attempt to bring the source under the gate was investigated by recessing the source/drain contacts by etching (see C. J. Koeneke et al., xe2x80x9cSchottky MOSFET for VLSIxe2x80x9d, IEDM, 367 (1981)). Sidewall spacers were still a limiting factor, however. This was improved by Snyder as described in U.S. Pat. No. 6,303,479, which also disclosed the ability to control vertical doping profiles without regard to horizontal profile control. The contacts were again made from PtSi.
U.S. Pat. No. 6,096,590 to Chan et al. describes a device in which the PtSi/Si junctions are not recessed. This yields a poor sub-threshold slope from reduced coupling of the gate at the edge of the channel. Exponential turn-on, indicative of the Schottky barrier being too high, is seen in measurements presented in the patent. Further, the gate-source capacitance will be high.
Recently, MOSFET devices having metal-semiconductor junctions between a source/drain and a channel have been demonstrated with sub-50 nm channel-lengths, using PtSi2 (see, e.g., C. Wang et al., xe2x80x9cSub-40 nm PtSi Schottky source/drain metal-oxide field-effect transistorsxe2x80x9d, Appl. Phys. Lett. 74, 1174 (1999); and A. Itoh et al., xe2x80x9cA 25-nm-long channel metal-gate p-type Schottky source/drain metal-oxide-semiconductor field-effect transistor on separation-by-implanted-oxygen substratexe2x80x9d, J. Journal Appl. Phys. Part 1 39, 4757 (2000)), ErSi2 (see, e.g., J. Kedzierski et al., xe2x80x9cComplementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regimexe2x80x9d, IEDM Tech. Dig., International Electron Devices Meeting 2000, San Francisco, Calif., p. 00-57 (2000); and W. Saitoh et al., xe2x80x9cAnalysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gatexe2x80x9d, J. Journal Appl. Phys. Part 1 38, 6226 (1999)), and CoSi2 (see, e.g., U. K. Matsuzawa et al., xe2x80x9cEnhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor field-effect transistorsxe2x80x9d, Appl. Phys. Lett. 76, 3992 (2000)) for the source/drain metal. Also, simulations have been performed all the way down to channel lengths of 10 nm (see, e.g., C. K. Huang et al., xe2x80x9cTwo-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nmxe2x80x9d, IEEE Trans. on Elect. Dev. 45, 842 (1998)), although a poor choice of device parameters limited the performance results, e.g., a large "PHgr"B. The performance of all of these devices is limited in part by the inability to control, and especially to lower, the height of the Shottkky barrier at the source and drain interfaces to the channel.
Only two disclosures of a non-silicide pure-metal/Si contact embodiment of a Schottky-barrier MOSFET have been found by the present inventors. Welch, U.S. Pat. No. 5,663,584, seems to describe Schottky barrier MOSFET systems and fabrication thereof; however, a contact of xe2x80x9cmetal or metal silicidexe2x80x9d is mentioned. This is inappropriate for fabrication of a device with a controlled barrier height. That is, there is no surface treatment or interface dielectric disclosed.
The disclosure by Hebiguchi in U.S. Pat. No. 5,801,398 is perhaps more practical, and a method for manufacturing a thin-film transistor such as for use in displays is presented. In this device (which is a field effect transistor or FET), the source/drain contacts to the Si channel are metal (a list of possibilities is presented), but again, no surface preparation is mentioned.
FIG. 1 shows the FET 100 that was discussed by Hebiguchi. The transistor contains a glass substrate 110, a gate electrode 120, a gate insulating film 130, a drain electrode 140, a source electrode 150, and a semiconductor active film 160. During operation, voltage is applied to the source electrode 150 and to the gate electrode 120. The voltage applied to the gate electrode 120 changes the electrical properties of the semiconductor active film 160 allowing current to flow from the source electrode 150 to the drain electrode 140. In particular, the voltage applied to the gate electrode 120 creates a channel-generating region 170, in the semiconductor active film 160 a short distance from the gate insulating film 130, through which current may flow.
Hebiguchi describes the semiconductor active film 160 as being hydrogenated amorphous silicon, the drain and source electrodes 140 and 150 are formed of conductive materials (metals) such as chromium (Cr), aluminum (Al), tantalum (Ta), platinum (Pt), gold (Au), tungsten (W), nickel (Ni), molybdenum (Mo), or certain mixtures of these materials, and the junctions between the semiconductor active film 160 and the source and drain electrodes 150 and 140 are insulating Schottky barriers. The metal selected for an n-channel thin film transistor is chosen on the basis of having a workfunction that is smaller than that of silicon and the metal selected for a p-channel thin film transistor has a workfunction that is larger than that of silicon.
A significant limitation with the transistor discussed in Hebiguchi, is the generally poor control over the Schottky barrier height. As is well known, use of different metals with widely varying work functions tends to result in Schottky barriers which vary in height over a dramatically reduced range. Further, no special effort is made in Hebiguchi to control or reduce extrinsic surface states.
Another type of junction to the channel is introduced by Yoshimura in U.S. Pat. No. 6,037,605, with the stated goal being to reduce short-channel effects. An oxide or nitride is disposed between Si source and drain contacts and a Si channel. The oxide is thicker farther away from the channel (down into the Si) to reduce currents not controlled by the gate. The thickness of the oxide is xe2x80x9csufficiently thin to permit charge tunnelingxe2x80x9d, and is disclosed to be 0.5 to 2.0 nm. This differs from the present invention, which is described in detail below, in several ways, for example the use of Si as a source/drain, as opposed to a metal.
A transistor includes a semiconductor channel disposed nearby a gate (e.g., separated therefrom by a dielectric) and disposed in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channelxe2x80x94interface layerxe2x80x94source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 xcexa9-xcexcm2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce the effects of intrinsic surface states in the semiconductor channel.